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Flexible static memory controller (FSMC)
RM0008
●
Write FIFO, 16 words long, each word 32 bits wide. This makes it possible to write to
slow memories and free the AHB quickly for other transactions. If a new transaction is
started to the FSMC, first the FIFO is drained
The FSMC registers that define the external device type and associated characteristics are
usually set at boot time and do not change until the next reset or power-up. However, it is
possible to change the settings at any time.
19.2
Block diagram
The FSMC consists of four main blocks:
●
●
●
●
The AHB interface (including the FSMC configuration registers)
The NOR Flash/PSRAM controller
The NAND Flash/PC Card controller
The external device interface
The block diagram is shown in Figure 19.3 .
19.3
19.3.1
AHB interface
The AHB slave interface enables internal CPUs and other bus master peripherals to access
the external static memories.
AHB transactions are translated into the external device protocol. In particular, if the
selected external memory is 16 or 8 bits wide, 32-bit wide transactions on the AHB are split
into consecutive 16- or 8-bit accesses.
The AHB clock (HCLK) is the reference clock for the FSMC.
Supported memories and transactions
General transaction rules
The requested AHB transaction data size can be 8-, 16- or 32-bit wide whereas the
accessed external device has a fixed data width. This may lead to inconsistent transfers.
Therefore, some simple transaction rules must be followed:
●
●
●
AHB transaction size and memory data size are equal
There is no issue in this case.
AHB transaction size is greater than the memory size
In this case, the FSMC splits the AHB transaction into smaller consecutive memory
accesses in order to meet the external data width.
AHB transaction size is smaller than the memory size
Asynchronous transfers may or not be consistent depending on the type of external
device.
410/995
–
–
Asynchronous accesses to devices that have the byte select feature (SRAM,
ROM, PSRAM).
In this case, the FSMC allows read/write transactions and accesses the right data
through its byte lanes BL[1:0]
Asynchronous accesses to devices that do not have the byte select feature (NOR
and NAND Flash 16-bit).
Doc ID 13902 Rev 9
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